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8705by www.idt.com rev. h july 2, 2010 1 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator g eneral d escription the ICS8705 is a highly versatile 1:8 differential-to- lvcmos/lvttl clock generator. the ICS8705 has two selectable clock inputs. the clk1, nclk1 pair can accept most standard differential input levels. the single ended clk0 input accepts lvcmos or lvttl input levels.the ICS8705 has a fully integrated pll and can be configured as zero delay buffer, multiplier or divider and has an input and output frequency range of 15.625mhz to 250mhz. the reference divider, feedback divider and output divider are each programmable, thereby allowing for the following out- put-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. the external feedback allows the device to achieve ?zero delay? between the input clock and the output clocks. the pll_sel pin can be used to bypass the pll for system test and debug purposes. in bypass mode, the reference clock is routed around the pll and into the internal output dividers. f eatures ? 8 lvcmos/lvttl outputs, 7 typical output impedance ? selectable clk1, nclk1 or lvcmos/lvttl clock inputs ? clk1, nclk1 pair can accept the following differential input levels: lvpecl, lvds, lvhstl, hcsl, sstl ? clk0 input accepts lvcmos or lvttl input levels ? output frequency range: 15.625mhz to 250mhz ? input frequency range: 15.625mhz to 250mhz ? vco range: 250mhz to 500mhz ? external feedback for ?zero delay? clock regeneration with configurable frequencies ? programmable dividers allow for the following output-to-input frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 ? fully integrated pll ? cycle-to-cycle jitter: 45ps (maximum) ? output skew: clk0, 65ps (maximum) clk1, nclk1, 55ps (maximum) ? static phase offset: 25 125ps (maximum), clk0 ? full 3.3v or 2.5v operating supply ? 0c to 70c ambient operating temperature ? lead-free package fully rohs compliant b lock d iagram p in a ssignment 32 31 30 29 28 27 26 25 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32-lead lqfp 7mm x 7mm x 1.4 mm y package top view v ddo q5 gnd q4 v ddo q3 gnd q2 sel0 sel1 clk0 nc clk1 nclk1 clk_sel mr v ddo q1 gnd q0 v ddo sel2 fb_in v dd q6 gnd q7 v ddo sel3 v dda pll_sel v dd ICS8705 pll_sel clk0 clk1 nclk1 clk_sel fb_in sel0 sel1 sel2 sel3 mr 0 1 q0 q1 q2 q3 q4 q5 q6 q7 pll 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8 2, 4, 8, 16, 32 , 64, 128 0 1
8705by www.idt.com rev. h july 2, 2010 2 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator t able 1. p in d escriptions t able 2. p in c haracteristics r e b m u ne m a ne p y tn o i t p i r c s e d 1 1 , 2 , 1 , 1 l e s , 0 l e s 2 l e s t u p n in w o d l l u p . 3 e l b a t n i s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 30 k l ct u p n in w o d l l u p. s l e v e l e c a f r e t n i l t t v l / s o m c v l . t u p n i k c o l c 4c n. t c e n n o c o n 51 k l ct u p n in w o d l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i - n o n 61 k l c nt u p n ip u l l u p. t u p n i k c o l c l a i t n e r e f f i d g n i t r e v n i 7l e s _ k l ct u p n in w o d l l u p . 1 k l c n , 1 k l c l a i t n e r e f f i d s t c e l e s , h g i h n e h w . t u p n i t c e l e s k c o l c . 0 k l c s o m c v l s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l 8r mt u p n in w o d l l u p e r a s r e d i v i d l a n r e t n i e h t , h g i h c i g o l n e h w . t e s e r r e t s a m h g i h e v i t c a l a n r e t n i e h t , w o l c i g o l n e h w . w o l o g o t s t u p t u o e h t g n i s u a c t e s e r . s l e v e l e c a f r e t n i l t t v l / s o m c v l . d e l b a n e e r a s t u p t u o e h t d n a s r e d i v i d 2 3 , 9v d d r e w o p. s n i p y l p p u s e r o c 0 1n i _ b ft u p n in w o d l l u p g n i t a r e n e g e r r o f r o t c e t e d e s a h p o t t u p n i k c a b d e e f l t t v l / s o m c v l . s t u p t u o e h t f o e n o o t t c e n n o c . " y a l e d o r e z " h t i w s k c o l c . s l e v e l e c a f r e t n i l t t v l / s o m c v l , 0 2 , 6 1 , 2 1 8 2 , 4 2 v o d d r e w o p. s n i p y l p p u s t u p t u o , 7 1 , 5 1 , 3 1 , 3 2 , 1 2 , 9 1 7 2 , 5 2 , 2 q , 1 q , 0 q , 5 q , 4 q , 3 q 7 q , 6 q t u p t u o 7 . t u p t u o k c o l c . e c n a d e p m i t u p t u o l a c i p y t . s l e v e l e c a f r e t n i l t t v l / s o m c v l 6 2 , 2 2 , 8 1 , 4 1d n gr e w o p. d n u o r g y l p p u s r e w o p 9 23 l e st u p n in w o d l l u p . 3 e l b a t n i s e u l a v r e d i v i d t u p t u o s e n i m r e t e d . s l e v e l e c a f r e t n i l t t v l / s o m c v l 0 3v a d d r e w o p. n i p y l p p u s g o l a n a 1 3l e s _ l l pt u p n ip u l l u p . s r e d i v i d e h t o t t u p n i s a k c o l c e c n e r e f e r d n a l l p e h t n e e w t e b s t c e l e s , h g i h n e h w . ) s s a p y b l l p ( k c o l c e c n e r e f e r e h t s t c e l e s , w o l n e h w . s l e v e l e c a f r e t n i l t t v l / s o m c v l . ) d e l b a n e l l p ( l l p s t c e l e s : e t o n p u l l u p d n a n w o d l l u p . s e u l a v l a c i p y t r o f , s c i t s i r e t c a r a h c n i p , 2 e l b a t e e s . s r o t s i s e r t u p n i l a n r e t n i o t r e f e r l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u c n i e c n a t i c a p a c t u p n i 4f p r p u l l u p r o t s i s e r p u l l u p t u p n i 1 5k r n w o d l l u p r o t s i s e r n w o d l l u p t u p n i 1 5k c d p e c n a t i c a p a c n o i t a p i s s i d r e w o p ) t u p t u o r e p ( v d d ,v o d d ,v a d d v 5 6 4 . 3 =3 2f p r t u o e c n a d e p m i t u p t u o 7
8705by www.idt.com rev. h july 2, 2010 3 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator t able 3a. pll e nable f unction t able s t u p n i s t u p t u o 0 = l e s _ l l p e d o m s s a p y b l l p 3 l e s2 l e s1 l e s0 l e s7 q : 0 q 00 0 0 8 00 0 1 8 00 10 8 00 1 1 6 1 0100 6 1 010 1 6 1 0110 2 3 0111 2 3 10 0 0 4 6 10 0 1 8 2 1 10 1 0 4 10 1 1 4 110 0 8 110 1 2 11 10 4 11 1 1 2 t able 3b. pll b ypass f unction t able s t u p n i s t u p t u o 1 = l e s _ l l p e d o m e l b a n e l l p 3 l e s2 l e s1 l e s0 l e s) z h m ( e g n a r y c n e u q e r f e c n e r e f e r7 q : 0 q 0000 0 5 2 - 5 2 11 000 1 5 2 1 - 5 . 2 61 00 10 5 . 2 6 - 5 2 . 1 31 00 11 5 2 . 1 3 - 5 2 6 . 5 11 0100 0 5 2 - 5 2 12 0101 5 2 1 - 5 . 2 62 0110 5 . 2 6 - 5 2 . 1 32 0111 0 5 2 - 5 2 14 10 0 0 5 2 1 - 5 . 2 64 10 0 1 0 5 2 - 5 2 18 10 10 5 2 1 - 5 . 2 62 x 10 1 1 5 . 2 6 - 5 2 . 1 32 x 1100 5 2 . 1 3 - 5 2 6 . 5 12 x 110 1 5 . 2 6 - 5 2 . 1 34 x 1110 5 2 . 1 3 - 5 2 6 . 5 14 x 1111 5 2 . 1 3 - 5 2 6 . 5 18 x
8705by www.idt.com rev. h july 2, 2010 4 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator t able 4a. p ower s upply dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, ta = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 3 1 . 33 . 35 6 4 . 3v v a d d e g a t l o v y l p p u s g o l a n a 5 3 1 . 33 . 35 6 4 . 3v v o d d e g a t l o v y l p p u s t u p t u o 5 3 1 . 33 . 35 6 4 . 3v i d d t n e r r u c y l p p u s r e w o p 6 9a m i a d d t n e r r u c y l p p u s g o l a n a 5 1a m i o d d t n e r r u c y l p p u s t u p t u o 0 2a m t able 4b. lvcmos / lvttl dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, ta = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n i e g a t l o v h g i h , l e s _ k l c , l e s _ l l p , 3 l e s , 2 l e s , 1 l e s , 0 l e s r m , n i _ b f 2v d d 3 . 0 +v 0 k l c2v d d 3 . 0 +v v l i t u p n i e g a t l o v w o l , l e s _ k l c , l e s _ l l p , 3 l e s , 2 l e s , 1 l e s , 0 l e s r m , n i _ b f 3 . 0 -8 . 0v 0 k l c3 . 0 -3 . 1v i h i t u p n i t n e r r u c h g i h l e s _ k l c , 0 k l c , n i _ b f , r m 3 l e s , 2 l e s , 1 l e s , 0 l e s v d d v = n i v 5 6 4 . 3 =0 5 1a l e s _ l l pv d d v = n i v 5 6 4 . 3 =5a i l i t u p n i t n e r r u c w o l l e s _ k l c , 0 k l c , n i _ b f , r m 3 l e s , 2 l e s , 1 l e s , 0 l e s v d d v , v 5 6 4 . 3 = n i v 0 =5 -a l e s _ l l pv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 6 . 2v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o d d , n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e h t n i . 2 / . " t i u c r i c t s e t d a o l t u p t u o v 3 . 3 " e e s a bsolute m aximum r atings supply voltage, v dd 4.6v inputs, v i -0.5v to v dd + 0.5 v outputs, v o -0.5v to v ddo + 0.5v package thermal impedance, ja 47.9c/w (0 lfpm) storage temperature, t stg -65c to 150c note: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only. functional operation of product at these conditions or any conditions be- yond those listed in the dc characteristics or ac character- istics is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability.
8705by www.idt.com rev. h july 2, 2010 5 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator t able 5a. ac c haracteristics , v dd = v dda = v ddo = 3.3v5%, ta = 0c to 70c t able 4c. d ifferential dc c haracteristics , v dd = v dda = v ddo = 3.3v5%, ta = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l cv d d v = n i v 5 6 4 . 3 =0 5 1a 1 k l c nv d d v = n i v 5 6 4 . 3 =5a i l i t n e r r u c w o l t u p n i 1 k l cv d d v , v 5 6 4 . 3 = n i v 0 =5 -a 1 k l c nv d d v , v 5 6 4 . 3 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 -v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o nv h i . s i 1 k l c n , 1 k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n v d d . v 3 . 0 + l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 5 2 6 . 5 10 5 2z h m p t h l , y a l e d n o i t a g a p o r p 1 e t o n ; h g i h - o t - w o l 0 k l c , v 0 = l e s _ l l p f 2 x q , z h m 0 5 2 57s n 1 k l c n , 1 k l c , v 0 = l e s _ l l p f 2 x q , z h m 0 5 2 53 . 7s n ) ? ( t ; t e s f f o e s a h p c i t a t s 4 , 2 e t o n 0 k l c , v 3 . 3 = l e s _ l l p f e r f 1 x q , z h m 0 0 2 0 0 1 -5 20 5 1s p 1 k l c n , 1 k l c , v 3 . 3 = l e s _ l l p f e r f 1 x q , z h m 7 6 1 5 1 -5 3 1 +5 8 2s p , v 3 . 3 = l e s _ l l p 1 x q , z h m 0 0 2 = f e r f 0 5 -0 0 1 +0 5 2s p 0 k l c , v 3 . 3 = l e s _ l l p 2 * x q , z h m 6 6 = f e r f 0 5 1 -5 2 -0 0 1s p 1 k l c n , 1 k l c , v 3 . 3 = l e s _ l l p 2 * x q , z h m 6 6 = f e r f 00 5 10 0 3s p t ) o ( k s ; w e k s t u p t u o 4 , 3 e t o n 0 k l cv 0 = l e s _ l l p5 6s p 1 k l c n , 1 k l cv 0 = l e s _ l l p5 5s p t ) c c ( t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y cf t u o z h m 0 4 >5 4s p t l e m i t k c o l l l p 1s m t r t / f e m i t l l a f / e s i r t u p t u o 0 0 40 5 9s p c d oe l c y c y t u d t u p t u o 3 47 5% , z h m 5 4 = n i f , e d o m 4 x l l p z h m 0 8 1 = t u o f 7 43 5% t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u t a t u p t u o e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n v o d d . 2 / e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n l a n g i s t u p n i k c a b d e e f e g a r e v a . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n v t a d e r u s a e m o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n
8705by www.idt.com rev. h july 2, 2010 6 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator t able 4d. p ower s upply dc c haracteristics , v dd = v dda = v ddo = 2.5v5%, ta = 0c to 70c t able 4f. d ifferential dc c haracteristics , v dd = v dda = v ddo = 2.5v5%, ta = 0c to 70c t able 4e. lvcmos / lvttl dc c haracteristics , v dd = v dda = v ddo = 2.5v5%, ta = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v d d e g a t l o v y l p p u s e r o c 5 7 3 . 25 . 25 2 6 . 2v v a d d e g a t l o v y l p p u s g o l a n a 5 7 3 . 25 . 25 2 6 . 2v v o d d e g a t l o v y l p p u s t u p t u o 5 7 3 . 25 . 25 2 6 . 2v i d d t n e r r u c y l p p u s r e w o p 0 9a m i a d d t n e r r u c y l p p u s g o l a n a 5 1a m i o d d t n e r r u c y l p p u s t u p t u o 0 2a m l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u v h i t u p n i e g a t l o v h g i h , l e s _ k l c , l e s _ l l p , 3 l e s , 2 l e s , 1 l e s , 0 l e s r m , n i _ b f 2v d d 3 . 0 +v 0 k l c2v d d 3 . 0 +v v l i t u p n i e g a t l o v w o l , l e s _ k l c , l e s _ l l p , 3 l e s , 2 l e s , 1 l e s , 0 l e s r m , n i _ b f 3 . 0 -8 . 0v 0 k l c3 . 0 -3 . 1v i h i t u p n i t n e r r u c h g i h l e s _ k l c , 0 k l c , n i _ b f , r m 3 l e s , 2 l e s , 1 l e s , 0 l e s v d d v = n i v 5 2 6 . 2 =0 5 1a l e s _ l l pv d d v = n i v 5 2 6 . 2 =5a i l i t u p n i t n e r r u c w o l l e s _ k l c , 0 k l c , n i _ b f , r m 3 l e s , 2 l e s , 1 l e s , 0 l e s v d d v , v 5 2 6 . 2 = n i v 0 =5 -a l e s _ l l pv d d v , v 5 2 6 . 2 = n i v 0 =0 5 1 -a v h o 1 e t o n ; e g a t l o v h g i h t u p t u o 8 . 1v v l o 1 e t o n ; e g a t l o v w o l t u p t u o 5 . 0v 0 5 h t i w d e t a n i m r e t s t u p t u o : 1 e t o n v o t o d d , n o i t c e s n o i t a m r o f n i t n e m e r u s a e m r e t e m a r a p e h t n i . 2 / . e r u g i f " t i u c r i c t s e t d a o l t u p t u o v 5 . 2 " e e s l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u i h i t n e r r u c h g i h t u p n i 1 k l cv d d v = n i v 5 2 6 . 2 =0 5 1a 1 k l c nv d d v = n i v 5 2 6 . 2 =5a i l i t n e r r u c w o l t u p n i 1 k l cv d d v , v 5 2 6 . 2 = n i v 0 =5 -a 1 k l c nv d d v , v 5 2 6 . 2 = n i v 0 =0 5 1 -a v p p e g a t l o v t u p n i k a e p - o t - k a e p 5 1 . 03 . 1v v r m c ; e g a t l o v t u p n i e d o m n o m m o c 2 , 1 e t o n 5 . 0 + d n gv d d 5 8 . 0 -v s a d e n i f e d s i e g a t l o v e d o m n o m m o c : 1 e t o nv h i . s i 1 k l c n , 1 k l c r o f e g a t l o v t u p n i m u m i x a m e h t , s n o i t a c i l p p a d e d n e e l g n i s r o f : 2 e t o n v d d . v 3 . 0 +
8705by www.idt.com rev. h july 2, 2010 7 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator t able 5b. ac c haracteristics , v dd = v dda = v ddo = 2.5v5%, ta = 0c to 70c l o b m y sr e t e m a r a ps n o i t i d n o c t s e tm u m i n i ml a c i p y tm u m i x a ms t i n u f x a m y c n e u q e r f t u p t u o 5 2 6 . 5 10 5 2z h m p t h l , y a l e d n o i t a g a p o r p 1 e t o n ; h g i h - o t - w o l 0 k l c , v 0 = l e s _ l l p f 2 x q , z h m 0 5 2 57s n 1 k l c n , 1 k l c , v 0 = l e s _ l l p f 2 x q , z h m 0 5 2 53 . 7s n ) ? ( t ; t e s f f o e s a h p c i t a t s 4 , 2 e t o n 0 k l c , v 5 . 2 = l e s _ l l p f e r f 1 x q , z h m 0 0 2 0 5 2 -5 20 0 2s p 1 k l c n , 1 k l c , v 5 . 2 = l e s _ l l p 1 x q , z h m 3 3 1 = f e r f 0 5 -0 0 10 5 2s p , v 5 . 2 = l e s _ l l p 1 x q , z h m 0 0 2 = f e r f 0 0 1 -0 0 1 +0 0 3s p 0 k l c , v 5 . 2 = l e s _ l l p 2 * x q , z h m 6 6 = f e r f 0 5 1 -5 2 -0 0 1s p 1 k l c n , 1 k l c , v 5 . 2 = l e s _ l l p 2 * x q , z h m 6 6 = f e r f 00 5 10 0 3s p t ) o ( k s ; w e k s t u p t u o 4 , 3 e t o n 0 k l cv 0 = l e s _ l l p5 6s p 1 k l c n , 1 k l cv 0 = l e s _ l l p5 5s p t ) c c ( t i j4 e t o n ; r e t t i j e l c y c - o t - e l c y cf t u o z h m 0 4 >5 4s p t ( t i j )5 , 4 e t o n ; r e t t i j e s a h p , v 5 . 2 = l e s _ l l p 2 * x q , z h m 6 6 = f e r f 0 5 s p t l e m i t k c o l l l p 1s m t r t / f e m i t l l a f / e s i r t u p t u o 0 0 40 5 9s p c d oe l c y c y t u d t u p t u o 3 47 5% , z h m 5 4 = n i f , e d o m 4 x l l p z h m 0 8 1 = t u o f 5 45 5% t a d e r u s a e m s r e t e m a r a p l l af x a m . e s i w r e h t o d e t o n s s e l n u t a t u p t u o e h t o t t n i o p g n i s s o r c t u p n i l a i t n e r e f f i d e h t m o r f d e r u s a e m : 1 e t o n v o d d . 2 / e h t d n a k c o l c e c n e r e f e r t u p n i e h t n e e w t e b e c n e r e f f i d e m i t e h t s a d e n i f e d : 2 e t o n l a n g i s t u p n i k c a b d e e f e g a r e v a . e l b a t s s i y c n e u q e r f e c n e r e f e r t u p n i e h t d n a d e k c o l s i l l p e h t n e h w . s n o i t i d n o c d a o l l a u q e h t i w d n a s e g a t l o v y l p p u s e m a s e h t t a s t u p t u o n e e w t e b w e k s s a d e n i f e d : 3 e t o n v t a d e r u s a e m o d d . 2 / . 5 6 d r a d n a t s c e d e j h t i w e c n a d r o c c a n i d e n i f e d s i r e t e m a r a p s i h t : 4 e t o n . d e s u e c r u o s t u p n i e h t n o t n e d n e p e d s i r e t t i j e s a h p : 5 e t o n
8705by www.idt.com rev. h july 2, 2010 8 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator d ifferential i nput l evel 2.5v c ore /2.5v o utput l oad ac t est c ircuit 3.3v c ore /3.3v o utput l oad ac t est c ircuit scope qx lvcmos 1.65v5% -1.165v5% o utput s kew c ycle - to -c ycle j itter o utput r ise /f all t ime scope qx lvcmos 1.25v5% -1.25v5% p arameter m easurement i nformation v cmr cross points v pp gnd clk nclk v dd t jit(cc) = t cycle n ? t cycle n+1 1000 cycles q0:q7 ? ? ? ? v ddo 2 v ddo 2 v ddo 2 t cycle n t cycle n+1 t sk(o) v ddo 2 v ddo 2 qy qx clock outputs 20% 80% 80% 20% t r t f gnd gnd v dd , v dda , v ddo v dd , v dda , v ddo
8705by www.idt.com rev. h july 2, 2010 9 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator o utput d uty c ycle /p ulse w idth /p eriod p ropagation d elay p hase j itter & s tatic p hase o ffset q0:q7 t pd v ddo 2 ? ? v dd 2 clk1 nclk1 clk0 t pw t period v ddo 2 v ddo 2 v ddo 2 t pw t period odc = q0:q7 (where t (?) is any random sample, and t (?) mean is the average of the sampled cycles measured on controlled edges) t (?) mean = static phase offset ? ? t (?) v oh v ol v oh v ol v ddo 2 nclk1 fb_in t jit(?) = t (?) ? t (?) mean = phase jitter clk1
8705by www.idt.com rev. h july 2, 2010 10 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator a pplication i nformation f igure 2. s ingle e nded s ignal d riving d ifferential i nput as in any high speed analog circuitry, the power supply pins are vulnerable to random noise. the ICS8705 provides sepa- rate power supplies to isolate any high switching noise from the outputs to the internal pll. v dd , v dda , and v ddo should be individually connected to the power supply plane through vias, and bypass capacitors should be used for each pin. to achieve optimum jitter performance, power supply isolation is required. figure 1 illustrates how a 10 resistor along with a 10f and a .01 f bypass capacitor should be connected to each v dda . p ower s upply f iltering t echniques f igure 1. p ower s upply f iltering 10 v dda 10 f .01 f 3.3v .01 f v dd figure 2 shows how the differential input can be wired to accept single ended levels. the reference voltage v_ref = v cc /2 is generated by the bias resistors r1, r2 and c1. this bias circuit should be located as close as possible to the input pin. the ratio w iring the d ifferential i nput to a ccept s ingle e nded l evels of r1 and r2 might need to be adjusted to position the v_ref in the center of the input voltage swing. for example, if the input clock swing is only 2.5v and v cc = 3.3v, v_ref should be 1.25v and r2/r1 = 0.609. v_ref r1 1k c1 0.1u r2 1k single ended clock input clk nclk vdd
8705by www.idt.com rev. h july 2, 2010 11 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator f igure 3c. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3b. clk/ n clk i nput d riven by 3.3v lvpecl d river f igure 3d. clk/ n clk i nput d riven by 3.3v lvds d river 3.3v r1 50 r3 50 zo = 50 ohm lvpecl zo = 50 ohm hiperclocks clk nclk 3.3v input r2 50 zo = 50 ohm input hiperclocks clk nclk 3.3v r3 125 r2 84 zo = 50 ohm 3.3v r4 125 lvpecl r1 84 3.3v d ifferential c lock i nput i nterface the clk /nclk accepts lvds, lvpecl, lvhstl, sstl, hcsl and other differential signals. both v swing and v oh must meet the v pp and v cmr input requirements. figures 3a to 3d show interface examples for the clk/nclk input driven by the most common driver types. the input interfaces suggested here are f igure 3a. clk/ n clk i nput d riven by lvhstl d river examples only. please consult with the vendor of the driver component to confirm the driver termination requirements. for example in figure 4a, the input termination applies for lvhstl drivers. if you are using an lvhstl driver from another ven- dor, use their termination recommendation. 1.8v r2 50 input lvhstl driver ics hiperclocks r1 50 lvhstl 3.3v zo = 50 ohm zo = 50 ohm hiperclocks clk nclk zo = 50 ohm r1 100 3.3v lvds_driv er zo = 50 ohm receiv er clk nclk 3.3v
8705by www.idt.com rev. h july 2, 2010 12 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator c4 0.1uf vdd vdd r4 1k zo = 50 vdd r7 10 - 15 vdd r2 43 rd1 not install (u1-24) (u1-32) logic input pin examples c3 0.1uf r5 1k sel2 c7 0.1uf to logic input pins (u1-9) vdd u1 ICS8705 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 32 31 30 29 28 27 26 25 sel0 sel1 clk0 nc clk1 nclk1 clk_sel mr vdd fb_in sel2 vddo q0 gnd q1 vddo q2 gnd q3 vddo q4 gnd q5 vddo vdd pll_sel vdda sel3 vddo q7 gnd q6 vdd=3.3v or 2.5v to logic input pins r4 43 vdd c16 10u pll_sel r1 43 c2 0.1uf zo = 50 zo = 50 (u1-12) (u1-16) (u1-28) sel3 sel1 ru2 not install vdda c1 0.1uf ro ~ 7 ohm driv er_lvcmos (u1-20) sel0 c5 0.1uf set logic input to '1' ru1 1k set logic input to '0' c6 0.1uf rd2 1k c11 0.01u l ayout g uideline the schematic of the ICS8705 layout example is shown in figure 4a. the ICS8705 recommended pcb board layout for this example is shown in figure 4b. this layout example is used as a general guideline. the layout in the actual system will depend on the selected component types, the density of the components, the density of the traces, and the stack up of the p.c. board. f igure 4a. ICS8705 lvcmos c lock g enerator s chematic e xample
8705by www.idt.com rev. h july 2, 2010 13 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator other signals gnd vdda r7 c7 50 ohm trace c11 via c16 pin 1 r2 u1 c5 50 ohm trace vdd r1 c2 c4 c6 c1 c3 f igure 4b. pcb b oard l ayout f or ICS8705 the following component footprints are used in this layout example: all the resistors and capacitors are size 0603. p ower and g rounding place the decoupling capacitors as close as possible to the power pins. if space allows, placement of the decoupling capacitor on the component side is preferred. this can reduce unwanted in- ductance between the decoupling capacitor and the power pin caused by the via. maximize the power and ground pad sizes and number of vias capacitors. this can reduce the inductance between the power and ground planes and the component power and ground pins. the rc filter consisting of r7, c11, and c16 should be placed as close to the v dda pin as possible. c lock t races and t ermination poor signal integrity can degrade the system performance or cause system failure. in synchronous high-speed digital systems, the clock signal is less tolerant to poor signal integrity than other signals. any ringing on the rising or falling edge or excessive ring back can cause system failure. the shape of the trace and the trace delay might be restricted by the available space on the board and the component location. while routing the traces, the clock signal traces should be routed first and should be locked prior to routing other signal traces. ? the differential 50 output traces should have same length. ? avoid sharp angles on the clock trace. sharp angle turns cause the characteristic impedance to change on the transmission lines. ? keep the clock traces on the same layer. whenever pos- sible, avoid placing vias on the clock traces. placement of vias on the traces can affect the trace characteristic impedance and hence degrade signal integrity. ? to prevent cross talk, avoid routing other signal traces in parallel with the clock traces. if running parallel traces is unavoidable, allow a separation of at least three trace widths between the differential clock trace and the other signal trace. ? make sure no other signal traces are routed between the clock trace pair. ? the series termination resistors should be located as close to the driver pins as possible.
8705by www.idt.com rev. h july 2, 2010 14 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator r eliability i nformation t ransistor c ount the transistor count for ICS8705 is: 3126 t able 6. ja vs . a ir f low t able for 32 l ead lqfp ja by velocity (linear feet per minute) 0 200 500 single-layer pcb, jedec standard test boards 67.8c/w 55.9c/w 50.1c/w multi-layer pcb, jedec standard test boards 47.9c/w 42.1c/w 39.4c/w note: most modern pcb designs use multi-layered boards. the data in the second row pertains to most designs.
8705by www.idt.com rev. h july 2, 2010 15 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator p ackage o utline - y s uffix for 32 l ead lqfp t able 7. p ackage d imensions reference document: jedec publication 95, ms-026 n o i t a i r a v c e d e j s r e t e m i l l i m n i s n o i s n e m i d l l a l o b m y s a b b m u m i n i ml a n i m o nm u m i x a m n 2 3 a - -- -0 6 . 1 1 a 5 0 . 0- -5 1 . 0 2 a 5 3 . 10 4 . 15 4 . 1 b 0 3 . 07 3 . 05 4 . 0 c 9 0 . 0- -0 2 . 0 d c i s a b 0 0 . 9 1 d c i s a b 0 0 . 7 2 d . f e r 0 6 . 5 e c i s a b 0 0 . 9 1 e c i s a b 0 0 . 7 2 e . f e r 0 6 . 5 e c i s a b 0 8 . 0 l 5 4 . 00 6 . 05 7 . 0 0 - - 7 c c c - -- -0 1 . 0
8705by www.idt.com rev. h july 2, 2010 16 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator t able 8. o rdering i nformation while the information presented herein has been checked for both accuracy and reliability, integrated device technology, inc. ( idt) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. no other circuits, patents, or licenses are impl ied. this product is intended for use in normal commercial and industrial applications. any other applications such as those requiring high reliability, or other extraordinary environmental requirement s are not recommended without additional processing by idt. idt reserves the right to change any circuitry or specifications without notice. idt does not authorize or warrant any idt product for use i n life support devices or critical medical instruments. r e b m u n r e d r o / t r a pg n i k r a me g a k c a pg n i g a k c a p g n i p p i h se r u t a r e p m e t y b 5 0 7 8y b 5 0 7 8 s c ip f q l d a e l 2 3y a r tc 0 7 o t c 0 t y b 5 0 7 8y b 5 0 7 8 s c ip f q l d a e l 2 3l e e r & e p a t 0 0 0 1c 0 7 o t c 0 f l y b 5 0 7 8f l y b 5 0 7 8 s c ip f q l " e e r f d a e l " d a e l 2 3y a r t r e p 0 5 2c 0 7 o t c 0 t f l y b 5 0 7 8f l y b 5 0 7 8 s c ip f q l " e e r f d a e l " d a e l 2 30 0 0 1c 0 7 o t c 0 . t n a i l p m o c s h o r e r a d n a n o i t a r u g i f n o c e e r f - b p e h t e r a r e b m u n t r a p e h t o t x i f f u s ? f l ? n a h t i w d e r e d r o e r a t a h t s t r a p : e t o n
8705by www.idt.com rev. h july 2, 2010 17 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator t e e h s y r o t s i h n o i s i v e r v e re l b a te g a pe g n a h c f o n o i t p i r c s e de t a d a1 m a r g a i d k c o l b d e t a d p u 2 0 / 5 2 / 1 b a 3 t a 5 t b 5 t ; f 4 t : d 4 t 3 5 7 , 6 n m u l o c e g n a r y c n e u q e r f e c n e r e f e r e h t d e s i v e r - e l b a t n o i t c n u f e l b a n e l l p m o r f w o r y c n e u q e r f t u p t u o e h t d e t a d p u - e l b a t s c i t s i r e t c a r a h c c a v 3 . 3 . x a m z h m 5 7 2 o t . x a m z h m 0 5 3 . s e l b a t v 5 . 2 d e d d a 2 0 / 4 1 / 3 c a 3 t a 5 t b 5 t 3 5 7 n m u l o c e g n a r y c n e u q e r f e c n e r e f e r e h t d e s i v e r - e l b a t n o i t c n u f e l b a n e l l p m o r f w o r y c n e u q e r f t u p t u o e h t d e t a d p u - e l b a t s c i t s i r e t c a r a h c c a v 3 . 3 . x a m z h m 0 5 2 o t . x a m z h m 5 7 2 m o r f w o r y c n e u q e r f t u p t u o e h t d e t a d p u - e l b a t s c i t s i r e t c a r a h c c a v 5 . 2 . x a m z h m 0 5 2 o t . x a m z h m 5 7 2 2 0 / 4 / 4 c1 t2 . s n o i t p i r c s e d n i p r e w o p d e s i v e r - e l b a t n o i t p i r c s e d n i p 2 0 / 0 1 / 4 c2 t2 c n i ) l a c i p y t ( f p 3 2 d d a - e l b a t s c i t s i r e t c a r a h c n i p d p . w o r2 0 / 5 1 / 7 c1 t2 " . 0 1 n i p o t t c e n n o c " d e c a l p e r , n o i t p i r c s e d m o r f 0 1 # n i p - e l b a t n o i t p i r c s e d n i p " . s t u p t u o e h t f o e n o o t t c e n n o c " h t i w 2 0 / 1 / 8 c1 t 2 8 . n o i t p i r c s e d r m d n a n o i t p i r c s e d 0 k l c d e s i v e r . m a r g a i d e m i t l l a f / e s i r t u p t u o d e s i v e r 2 0 / 1 2 / 8 d d 4 t , a 4 t , 1 t b 5 t , a 5 t 6 , 4 , 2 7 , 5 v r o f n o i t p i r c s e d d e s i v e r d d . y l p p u s e v i t i s o p m o r f y l p p u s e r o c d a e r o t s n o i t i d n o c t s e t t n e r e f f i d h t i w " c d o " o t w o r r e h t o n a d e d d a , s c i t s i r e t c a r a h c c a . s e u l a v d n a . t a m r o f d e t a d p u 2 0 / 2 2 / 1 1 e 1 b 5 t & a 5 t 2 7 & 5 . n o i t p i r c s e d r m d e s i v e r - e l b a t n o i t p i r c s e d n i p . 1 k l c n , 1 k l c r o f s t i m i l t e s f f o e s a h p c i t a t s e h t d e g n a h c - s e l b a t c a 3 0 / 2 2 / 1 f b 5 t & a 5 t7 & 5 . " 2 * x q , z h m 6 6 = f e r f " h t i w t e s f f o e s a h p c i t a t s d e d d a - s e l b a t c a 4 e t o n d a e r o t r e t e m a r a p o p s n i o p y t d e t c e r r o c - e l b a t c a v 3 . 3 . 7 e t o n m o r f " . . . l t t v l / s o m c v l - o t - l a i t n e r e f f i d . . . " d a e r o t e l t i t d e s i v e r t e e h s a t a d t u o h g u o r h t 3 0 / 3 1 / 2 g b 5 t7 9 . 5 e t o n d n a , c e p s r e t t i j e s a h p d e d d a - e l b a t s c i t s i r e t c a r a h c c a v 5 . 2 . m a r g a i d o p s & r e t t i j e s a h p h t i w m a r g a i d t e s f f o e s a h p c i t a t s d e c a l p e r 3 0 / 4 1 / 3 g 2 t2 1 1 c d e g n a h c - e l b a t s c i t s i r e t c a r a h c n i p n i . l a c i p y t f p 4 o t . x a m f p 4 m o r f . n o i t c e s e c a f r e t n i t u p n i k c o l c l a i t n e r e f f i d d e d d a 3 0 / 5 1 / 5 g3 1 & 2 1e n i l e d i u g t u o y a l d e d d a 3 0 / 6 / 6 g6 t4 1r e b m u n t r a p " e e r f - d a e l " d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 4 0 / 6 1 / 6 g 8 t 1 6 1 . t e l l u b e r u t a r e p m e t d e d d a - n o i t c e s s e r u t a e f . e t o n " e e r f - d a e l " d e d d a - e l b a t n o i t a m r o f n i g n i r e d r o 5 0 / 8 1 / 3 h8 t 6 1 8 1 . s c i m o r f t d i h t i w r e t o o f / r e d a e h s ' t e e h s a t a d d e t a d p u . n m u l o c r e b m u n r e d r o / t r a p m o r f x i f e r p " s c i " d e v o m e r . e g a p t c a t n o c d e d d a 0 1 / 2 / 7
8705by www.idt.com rev. h july 2, 2010 18 ICS8705 z ero d elay , d ifferential - to -lvcmos/lvttl c lock g enerator we?ve got your timing solution. sales 800-345-7015 (inside usa) +408-284-8200 (outside usa) fax: 408-284-2775 tech support netcom@idt.com 6024 silver creek valley road san jose, ca 95138 ? 2010 integrated device technology, inc. all rights reserved. product specifications subject to change without notice. idt, th e idt logo, ics and hiperclocks are trademarks of integrated device technology, inc. accelerated thinking is a service mark of integrated device technology, inc. all other brands, product names and marks are or m ay be trademarks or registered trademarks used to identify products or services of their respective owners. printed in usa

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